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NXP Semiconductors
LPC11C12/C14
[6]
[7]
[8]
[9]
The maximum t f for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA
output stage t f is specified at 250 ns. This allows series protection resistors to be connected in between the
SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified t f .
In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors
are used, designers should allow for this when considering bus timing.
The maximum t HD;DAT could be 3.45 μ s and 0.9 μ s for Standard-mode and Fast-mode but must be less than
the maximum of t VD;DAT or t VD;ACK by a transition time (see UM10204 ). This maximum must only be met if
the device does not stretch the LOW period (t LOW ) of the SCL signal. If the clock stretches the SCL, the
data must be valid by the set-up time before it releases the clock.
t SU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in
transmission and the acknowledge.
[10] A Fast-mode I 2 C-bus device can be used in a Standard-mode I 2 C-bus system but the requirement t SU;DAT =
250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period
of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line t r(max) + t SU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I 2 C-bus
specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
t f
t SU;DAT
SDA
70 %
30 %
70 %
30 %
t f
t HD;DAT
t H IGH
t VD;DAT
SCL
70 %
30 %
70 %
30 %
70 %
30 %
70 %
30 %
t LOW
S
1 / f SCL
002aaf425
Fig 19. I 2 C-bus pins clock timing
10.6 SPI interfaces
Table 14.
Dynamic characteristics of SPI pins in SPI mode
Symbol
T cy(PCLK)
T cy(clk)
Parameter
PCLK cycle time
clock cycle time
Conditions
[1]
Min
20
40
Typ
-
-
Max
-
-
Unit
ns
ns
SPI master (in SPI mode)
t DS
data set-up time
in SPI mode
[2]
27
-
-
ns
2.0 V ≤ V DD ≤ 3.6 V
1.8 V ≤ V DD < 2.0 V
36
-
-
ns
t DH
data hold time
in SPI mode
[2]
0
-
-
ns
t v(Q)
t h(Q)
data output valid time in SPI mode
data output hold time in SPI mode
[2]
[2]
-
0
-
-
10
-
ns
ns
SPI slave (in SPI mode)
t DS
data set-up time
in SPI mode
[3][4]
0
-
-
ns
LPC11C12_C14_0
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 00.05 — 23 April 2010
? NXP B.V. 2010. All rights reserved.
37 of 49
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